The storage cells of EEPROMs are generally formed by floating-gate storage transistors and a selection transistor used to connect the storage transistor to a word line and a bit line. The EEPROMs use the principle of the non-volatile storage of charges at the floating gate of the floating-gate transistor. Conventionally, the writing (the term programming is also used) is done by the injection, by the tunnel effect, of electrons from the drain or the source into the floating gate (or from the floating gate into the drain or the source). The erasure is done by the injection, by the tunnel effect, of electrons from the floating gate into the drain or the source (or from the drain or the source into the floating gate).
There are also known EEPROMs called Flash-EEPROMs. In these memories, there is no selection transistor and the storage transistors are directly connected to the word lines and bit lines. In this case, a total erasure is carried out for the storage cells. This type of memory enables the reduction of the size of the memory for an equivalent storage capacity.
The injection of electrons from the drain (or source) into the floating gate of a storage transistor is done conventionally by grounding the drain (or source) of this transistor, applying a relatively high positive voltage (of about +15 volts) to its control gate to create an attraction field, and applying a moderate positive voltage (of 6 to 9 volts) at the source (or drain) to generate hot electrons. When a sufficiently large number of electrons has collected at the floating gate, the potential of the floating gate reaches the threshold potential of the transistor and prevents the passage of current in a read mode.
The injection of electrons from the floating gate into the drain (or source) is done by the application of a relatively high positive voltage (+15 volts) to the drain (or source), the control gate of the storage transistors being ground connected, and the source (or the drain) being left floating. The negative charges are then extracted from the floating gate and directed towards the drain (or source) by the Fowler-Nordheim effect. The thickness of the oxide between the floating gate and the drain (or the source) must be sufficiently low (about 100 Angstroms or less) to enable the injection by Fowler-Nordheim effect.
This type of memory has drawbacks, especially in the implementation of the ejection of the electrons from the floating gates:
the drain-substrate (or source-substrate) current during the ejection is relatively great and in practice, for large-capacity memories, makes it necessary to have a high positive voltage source that is external to the circuit, PA1 a relatively high reverse voltage is generated between the drains (or sources) and the substrate during the ejection. In practice, this dictates the use of drains (or sources) with dual diffusion, which reduces the density of implantation of the cells, and PA1 the application of a relatively high positive voltage during the erasure at the drains (or the sources) increases the probability of the creation of hot holes by an avalanche effect on the surface of the drain-substrate junction (or source-substrate junction). These holes are trapped in the thin oxide located beneath the floating gate.
For further details on these phenomena, reference may be made to the U.S. Pat. No. 5,077,691 by Advanced Micro Devices Inc. In this patent, it is proposed to erase the cells by the application of a relatively high negative voltage (-12 to -17 volts) to the control gates, a relatively low positive voltage (+0.5 to +5 volts) being applied on the sources, the substrate being connected to the ground, and the drains being left in a state of high impedance. Thus, it is possible to induce a Fowler-Nordheim effect, while at the same time keeping the reverse source-substrate voltage below +5 volts. The leakage current from the source to the substrate is reduced, enabling the memory to be supplied with a single external positive voltage source (+5 volts). Furthermore, this enables the use of sources comprising only one diffusion. This limits the surface area of the cells. Finally, it is possible to eliminate the creation of hot holes, thus increasing the reliability of the memory.
To reduce the voltages needed for the programming and erasure in terms of absolute value, the patent application EP-A-0 750 313 discloses a memory organized in words with a duplication of the word line. Thus, in this application, a P type transistor is associated with each word to control the gate of the floating-gate transistor. However, it appears to be necessary to add a second selection transistor to bias the gate of the floating-gate transistors when they are not controlled to obtain a more reliable memory.